Active Load

in this lecture we are going to start looking at a particular type of circuit that is going to try to maximize the gain available from an amplifier so so far you would have seen that the common source amplifier gives you the maximum available gain that you can get so you will need a bias voltage v b at the gate of the transistor and the small signal is also applied here the output is of course taken at the drain so maybe i will call this the d c voltage is capital v o plus the a c voltage is small v o so we know that the gain of this circuit v o by v s is minus g m r now suppose i want to get more and more gain from the circuit i will need to either increase the g m of the circuit or increase the resistance of the circuit now there is a limit to which you can gain increase the g m primarily because you dont want to keep increasing the power ah by increasing the current so if i want to increase g m i need to increase current which means power consumption would increase i do not want to do that ah the other thing that i would need to do is increase the width to length ratio the otherwise i would need to increase the otherwise if i wanted to increase g m if i wanted to increase if i wanted to increase the gain of the circuit so this is a i increase a in two ways i need to increase g m or increase r now i can increase g m by increasing the current or increasing the w over l of the transistor now all of these has both of these have certain issues if i increase i of course i am increasing the power consumption of the circuit which i do not want to do if i increase the width and length of width over length of the device i am actually making the device slower because i am increasing the capacitance of the device so the band width gets affected so this affects power and this affects band width i do not want to affect either of these as much as possible if i increase r what happens suppose i keep the current consumption constant and width and length of the transistor constant ah if i increase r what i find is that v o the d c value is v d d minus i naught r so if i keep increasing the value of resistance ah this keep drop reducing so the d c voltage at the gate of at the drain of transistor keeps reducing eventually whereas the v b stays constant because the current is constant so far you would have seen this type of common source amplifier and you can write down the various d c voltages in terms of the d c currents and so on ah but the voltage that we are interested in is the output d c voltage which is v d d minus i naught r and we know that for this circuit the small signal gain v o by v s is minus g m r now let us say that we are trying to ah increase this gain the magnitude of this gain so this is what we are going to try to do now ah there are of course only two ways two parameters that you can touch so you can increase the transconductance so this can be done in two ways ah i can increase i d which i do

not want to do which because this will increase power this increases the d c power consumption which i do not want to do the other way i can increase g m is to increase the widths over length ration and this will increase capacitance increase its capacitance and of course more importantly decreases the band width which is also a problem i want to keep the band width constant and the other way to increase the magnitude of v o by v s is to increase the value of resistance now on the phase of it this seems fine but please note that the output d c voltage reduces linearly with increase in resistance in other words ah the actual implication of this is that m one moves closer to the triode region to the triode boundary and therefore what i am actually giving up is swing limit and this is this is this is also a problem now let us show this graphically so that we get a better understanding i am going to show this on the plot of i d versus v d s so we know that for a particular v b the i d versus v d s plot looks like this and initially i might have been biased somewhere here v d d minus i naught r d but now if i increase r for the same v b i will move closer and closer to the triode lets say this was the triode boundary i will move closer and closer to the triode boundary which i do not want to do now it turns out that you need a large value of resistance without changing the bias voltage at the output you may remember from your basic circuit course that if you take an nmos transistor and bias it using a current source the gain of the circuit so v o by v s is nothing but minus g m r d s and this is the intrinsic gain of nmos so you may remember that ah this is the largest gain that you can get from a transistor so what we want to achieve is we want to you get a common source amplifier which has a gain that is as close to this is possible this of course does not have strong limitations on output bias point because the current source can have a large range of voltages across it without changing the current now our job next is going to be to design this is ah going to be to design this current source now what we want is we actually want a current source of some value i naught right so this was i naught now please note that the current source is taking some current from v d d and pushing it to ground and obviously it has a constant voltage independent of v o which means that r volt is large so these are the characteristics you want from a current source so many of you might realize that a pmos transistor with its source connected to v d d and its drain connected to some v b one i will call it ah v b one or or v b two which is gate connected to v b two will have a current i naught that is related to v b two in the following manner

in this way right so i need to choose v b two and w over l of the pmos transistor such that it has a current i naught what is the output resistance seen at the drain this is of course the r d s of the pmos which is which can be designed to be very large so now we are going to replace the current source with a pmos transistor that has biased for a particular current so this is the amplifier that you have been looking for so let us say the nmos transistor is m one and the pmos transistor is m two and i am going to say that the nmos transistor has a bias voltage v b one and ah signal voltage v s applied to the gate the pmos transistor has some voltage v b two at its gate now you need to apply a voltage v b one such that the nmos transistor has a current i naught and you need to apply a v b two such that the pmos transistor also carries a current i naught if you were to draw the small signal equivalent circuit so ah before we draw the small signal equivalent circuit i want to emphasize again that v b one and v b two have to be chosen very carefully so that the two transistors have the same current i naught and there is one additional condition that is very important i will write it down both m one and m two are in saturation this is a very important condition as you will see so you need to choose v b one and v b two very carefully now let us draw the small signal equivalent circuit so i have a voltage v s which is applied to the gate of m one and there is a current source which is g m one v g s one and r d s one of m one so this is the drain of m one this is of course the source of m one now please note that the drain of m one is connected to the drain of m two which is also happens to be the output voltage v o now what happens to the current source of ah m two the voltage control current source clearly the small signal voltage at both the source and the gate of the pmos transistor is zero and therefore there will be no signal current ah generated by the g m portion of the pmos transistor now you can write the expression for v o by v s this is nothing but minus g m into r d s one parallel r d s two so now this can be very very large and in fact this is ah only around half of the intrinsic gain of the transistor ah this can be much larger than g m times r because the value of r d s is normally much larger than the value of r what about the bias point please note that the output voltage v o d c ok is not limited by r d s of the pmos transistor so this is an important distinction compared to the case with the resistor where the output d c voltage was related to ah the value of the resistance in the case of the pmos transistor the output bias voltage can vary over a large range of

values without affecting the value of the current or the ah ah or the ah performance of the pmos transistor now we can go one step further to complete this whole scenario we can go one step further ah of course you can also imagine a scenario where ah you use the pmos transistor for getting some signal gain also so what do i mean by that in the earlier case i was applying v s here and i was connecting the gate of the pmos transistor to small signal ground but a question can be asked why not connect the gate of the pmos transistor to v s so that you get small signal gain from the pmos transistor also and yes definitely this can be done so let us look at that circuit so i am going to this is the circuit ah that will have v s being applied to the gate of both nmos and pmos and i will leave this as a home work but you can draw the small signal equivalent circuit and show that v o by v s will be minus g m one plus g m two times r d s one parallel r d s two so the gain of this circuit will be even higher than the gain of the previous circuit ah before we proceed further with this circuit i just want to point out that this particular style of using a pmos transistor to get more gain ah you call this particular pmos transistor by a specific name this pmos transistor is called an active load so instead of using a passive resistor a small signal passive resistor which is passive the pmos transistor actually has small signal gain so from a small signal point of view it is active and this is such a way of using the circuit is called an active load now in this for this particular circuit each transistor acts as an active load for the other transistor now an important condition is that both m one and m two should be in saturation so only if both of them are in saturation will you actually get large gain if any one of them goes into the triode region you will not get large gain either for this circuit or for the previous circuit those of you who would have taken a course on digital integrated circuits will know that this circuit is actually used in digital design not in a small signal fashion as the cmos inverter in those cases you do not apply a small signal voltage at the input and ah you dont take a small signal voltage at the output and i encourage all of you to go back and draw the v out versus v in d c characteristics for this circuit so if you were to take this circuit and apply a d c voltage v in and look at the output d c voltage v out if you plot v in versus v out i will give you the curve here i encourage you all to study the circuit and analyze how this happens so v in is normally varied between zero and v d d so if you quickly ah look at the circuit when v in is very small ah below the threshold voltage of the nmos transistor the nmos transistor is completely cut off and it cannot conduct any current and therefore the pmos transistor also has to be ah ah a nonconductive however the source gate voltage for the pmos transistor is very large so therefore the only way this can happen is if the drain source voltage or the source drain voltage of the pmos transistor is almost zero so what you will find is that the output voltage till the nmos transistor turns on the output voltage will remain at v d d there is no current through

the circuit so the output voltage cannot change and the drain source voltage for the pmos transistor is clearly zero it is v d d minus v naught after the input voltage crosses v t n ah you will find that the nmos can conduct because the v out is very large the nmos will be in saturation region but the pmos will be in triode region now before i draw the center portion let us look at the other side if you look at voltages between v d d minus v t p and v d d you will find that the circuit is not conductive because the pmos transistor is off and so you will find that the output voltage is zero and stays zero because the nmos transistor is has the drain source voltage of zero eventually the nmos transistor hits triode and it starts to conduct with the pmos transistor being in saturation now there is the center portion where both transistors are in saturation now this portion is the analog portion in this region both m one and m two are in saturation and this is where you get maximum gain because please note that the gain a which is v o by v s is nothing but the ah slope of this curve it is basically d v o by d v in of course i have shown this is in an exaggerated manner ah such that the gain is not very high okay ah if you actually look at a typical cmos inverter ah if you look at it a digital i c text book you may actually see a curve that looks more like this i have exaggerated the curve ah to show that ah you know you get large gain you can actually get ah in an ideal case a cmos inverter should look like this this is the kind of curve you will see if you ignore channel length modulation so this slope is minus infinity if you ignore lambda slope is minus infinity in other words the gain is infinite clearly because r d s is infinite i have shown a case where lambda is very small ah sorry lambda is very large for the curve shown for an ideal transistor lambda is zero when you will have r d s equal to infinity so there is a range of output and input voltages over which the transistor ah both transistors are in saturation this is called the cmos inverter and this can also be used to bias the ah this can also be used to get very large gains